SY120-GBM

Ganymed chip

Functional description

Overview

Revolutionized New Platform for All Integrated Smart & Secure Sensors

Next generation applications in logistics, robotics, automation, smart home and building, consumer and white goods, smart city and renewable energy require the adaption of smart and secure sensors with data connectivity. Existing semiconductor standard solutions often provide insufficient flexibility and missing software environment. The most critical item, however, is the missing inherent data security approach encompassing the complete value chain of the product.

The Solution

Sensry is a newly established company offers an smart edge sensor construction kit with highly flexible and customizable hardware configurations according to customer requirements. The universal sensor platform USeP combines cutting-edge assembly and packaging technologies with new design methods as well as various integration possibilities for sensors.

Features of the Generic Base Module (GBM)

  • Top level interface for extension PCB (i.e. sensors)
  • Support of multiple communication standards
  • Low power consumption
  • Multi-Core RISC-V performance for smart edge computing
  • Adequate memory resources
  • Inherent multi-layer data security and authentication
  • Fast design using standard library HW components
  • Smallest form factor due to advanced 3D-packaging
  • SDK & Toolchain available
  • Integration in fog, edge and cloud computing
  • Optional integration support from Sensry

Key Features

  • Processing Unit
    • RISC-V based cluster core (max. 400MHz)
    • 1 RISCY Data acquisition Unit (DAQU)
    • 8 RISCY Data Proc. Units (DPU) with FPU
    • Event bus
    • DMA
  • Security features
    • Crypto Co-Processor
    • Secure Boot ROM
    • Secure MRAM / SRAM
    • True Random Number Generator (TRNG)
    • One-Time-Programmable Memory (OTP) for Keys and Certificates
  • Interfaces
    • 3x UART (up to 2Mbit/s, two of them with hardware handshake)
    • 4x I2C (up to 400kHz)
    • 4x I2S
    • 7x SPI (up to 50MHz)
    • CAN-FD
    • RGMII with MDIO for Ethernet-Phy
    • HyperBus (for external RAM/Flash)
    • Debug JTAG
    • 25MS/s 12bit SAR ADC
    • 100kS/s 11bit ultra low power SAR ADC
    • 16Bit Sigma Delta ADC (Audio)
    • 32 GPIO (configurable for 1.8V or 3.3V operation)
    • Each interface (except GPIO) can be induvidually disabled for power saving
  • Memory
    • 512kB Secure MRAM
    • 512kB MRAM
    • 4MB SRAM
    • Individual Data & Instruction Cache for the DPU

Interfaces

The 3D-System-in-Package provides numerous interfaces to the Top- and Bottom-Level.

core interfaces to Top- and Bottom-Level

The system has digital and analog interfaces to connect sensor devices to the system. There are three different Analog-to-Digital converters integrated. Two complex wired interfaces are supported by the Ganymed® core: Ethernet TSN and CAN-FD. These communication interfaces require an external physical layer. All interfaces are described in separate sections.

The Bottom-Level is the interface to the embedded customer system in form of a BGA-144 footprint with a pitch of 0.8mm and a ball diameter of 0.4mm. Please refer to section to find the footprint dimensions. The interface distribution is divided into several power and management pins and the I/ O interface. Figure 4 shows the general pin out of the device from top view

The Top-Level is the interface to the Package-on-Package sensor or peripheral parts. The application specific sensors are assembled on top side of the sensor PCB. The bottom side of the sensor PCB is the interface to the Ganymed® system. The interface includes power sources and different digital and analog interfaces. The Top-Level Figure 5 illustrates the different available interfaces.

Pin definitions

Top Level Footprint

Top-Level available interfaces
PadBlockSignalVoltageNote
PT7SPI0SCK1.8 VSystem Clock
PT6SPI0SDO1.8 VData Out
PT5SPI0SDI1.8 VData In
PT9SPI0nCS01.8 VChip Select 0 (low active)
PT8SPI0nCS11.8 VChip Select 1 (low active)
PT12SPI1SCK1.8 VSystem Clock
PT11SPI1SDO1.8 VData Out
PT10SPI1SDI1.8 VData In
PT14SPI1nCS01.8 VChip Select 0 (low active)
PT13SPI1nCS11.8 VChip Select 1 (low active)
PR16SPI2SCK1.8 VSystem Clock
PT16SPI2SDO1.8 VData Out
PT15SPI2SDI1.8 VData In
PN16SPI2nCS01.8 VChip Select 0 (low active)
PP16SPI2nCS11.8 VChip Select 1 (low active)
PK1QSPISCK1.8 VSystem Clock
PJ1QSPISDIO01.8 VData0
PH1QSPISDIO11.8 VData1
PG1QSPISDIO21.8 VData2
PF1QSPISDIO31.8 VData3
PL1QSPICS1.8 VChip Select
PT4I2C0SCL1.8 VClock
PT3I2C0SDA1.8 VData
PT2I2C3SCL1.8 VClock
PT1I2C3SDA1.8 VData
PH16I2S0SCK1.8 VClock
PG16I2S0SDI1.8 VData In
PJ16I2S0SWS1.8 VWord Select
PL16I2S1SCK1.8 VClock
PK16I2S1SDI1.8 VData In
PM16I2S1SWS1.8 VWord Select
PR1UART1RX1.8 VReceive
PP1UART1RX1.8 VReceive
PN1UART1RTS1.8 VReady to Send
PM1UART1CTS1.8 VClear to Send
PF16GPIO01.8 V
PE16GPIO11.8 V
PD16GPIO21.8 V
PC16GPIO31.8 V
PB16GPIO181.8 V
PA16GPIO191.8 V
PA15GPIO201.8 V
PA14GPIO211.8 V
PA5HS-ADC0VIN_PAnalogHigh Speed ADC VIN_P 0
PA4HS-ADC0VIN_NAnalogHigh Speed ADC VIN_N 0
PA2HS-ADC1VIN_PAnalogHigh Speed ADC VIN_P 1
PA1HS-ADC1VIN_NAnalogHigh Speed ADC VIN_N 1
PA10LP-ADCVIN_PAnalogLow Power ADC VIN_P
PA11LP-ADCVIN_NAnalogLow Power ADC VIN_N
PA6HP-ADCVIN_PAnalogHigh Precision ADC VIN_P
PA3HP-ADCVIN_NAnalogHigh Precision ADC VIN_N
PA7RESReservedAnalogReserved Pin
PA9RESReservedAnalogReserved Pin
PD1VDD IO3.3V3.3V Supply
PE1VDD IO1.8V1.8V Supply
PC1VSS IOGNDDigital GND
PA13VDDA1.8V1.8V Analog Supply
PA12VSSAGNDAnalog GND
PB1Spare ThroughSpare Through between PCB and Package Top Level

All the described signals and power supplies can be access on the top level. Any kind of digital or analog component which fits onto the size of the chip can be assembled on the Package Top-Level PCB.

Bottom Level Footprint

Bottom-Level Footprint

Notes:

  1. Additional physical layer is needed to use the CAN or Ethernet TSN (RGMII) interface
  2. The ADC0 and ADC4 interfaces are parallel connected High-Speed-ADC, Low-Power-ADC and High-Precision-ADC input:
    • ADC0-VIN_P = HS-ADC0-VIN_P = LP-ADC-VIN_P = HP-ADC-VIN_P
    • ADC0-VIN_N = HS-ADC0-VIN_N = LP-ADC-VIN_N = HP-ADC-VIN_N

PadBlockSignalVoltageNote
K6UART0TX1.8 VTransmit
L6UART0RX1.8 VReceive
N7UART2TX3.3 VTransmit
L7UART2RX3.3 VReceive
M7UART2RTS3.3 VReady to Send
H8UART2CTS3.3 VClear to Send
N11SPI3SCK1.8 VSystem Clock
M9SPI3SDO1.8 VData Out
L9SPI3SDI1.8 VData In
M10SPI3nCS01.8 VChip Select 0 (low active)
L10SPI3nCS11.8 VChip Select 1 (low active)
M11SPI4SCK1.8 VSystem Clock
N13SPI4SDO1.8 VData Out
M12SPI4SDI1.8 VData In
N12SPI4nCS01.8 VChip Select 0 (low active)
L12SPI4nCS11.8 VChip Select 1 (low active)
M13SPI5SCK3.3 VSystem Clock
L11SPI5SDO3.3 VData Out
K10SPI5SDI3.3 VData In
L13SPI5nCS03.3 VChip Select 0 (low active)
F8SPI5nCS13.3 VChip Select 1 (low active)
K11SPI6SCK3.3 VSystem Clock
J10SPI6SDO3.3 VData Out
D7SPI6SDI3.3 VData In
E7SPI6nCS03.3 VChip Select 0 (low active)
J12SPI6nCS13.3 VChip Select 1 (low active)
N10I2C1SCL1.8 VClock
K8I2C1SDA1.8 VData
N9I2C2SCL3.3 VClock
L8I2C2SDA3.3 VData
N8I2C3SCL1.8 VClock - I2C3 is additionally available on Sensor Level
M8I2C3SDA1.8 VData - I2C3 is additionally available on Sensor Level
A11GPIO41.8 VGeneral Purpose I/O and PWM
C11GPIO51.8 VGeneral Purpose I/O and PWM
A13GPIO61.8 VGeneral Purpose I/O and PWM
B12GPIO71.8 VGeneral Purpose I/O and PWM
D10GPIO83.3 VGeneral Purpose I/O and PWM
C12GPIO93.3 VGeneral Purpose I/O and PWM
B13GPIO103.3 VGeneral Purpose I/O and PWM
C13GPIO113.3 VGeneral Purpose I/O and PWM
F10GPIO123.3 VGeneral Purpose I/O and PWM
F11GPIO133.3 VGeneral Purpose I/O and PWM
F12GPIO143.3 VGeneral Purpose I/O and PWM
E13GPIO153.3 VGeneral Purpose I/O and PWM
B10GPIO161.8 VGeneral Purpose I/O and PWM
B11GPIO171.8 VGeneral Purpose I/O and PWM
B9GPIO221.8 VGeneral Purpose I/O and PWM
A10GPIO231.8 VGeneral Purpose I/O and PWM
E10GPIO241.8 VGeneral Purpose I/O and PWM
E11GPIO251.8 VGeneral Purpose I/O and PWM
E12GPIO261.8 VGeneral Purpose I/O and PWM
D11GPIO271.8 VGeneral Purpose I/O and PWM
D12GPIO281.8 VGeneral Purpose I/O and PWM
A12GPIO291.8 VGeneral Purpose I/O and PWM
D13GPIO301.8 VGeneral Purpose I/O and PWM
C10GPIO311.8 VGeneral Purpose I/O and PWM
M3RGMII1TXC1.8 VReduced Gigabit Media Independent Interface
L4RGMII1TXD01.8 VReduced Gigabit Media Independent Interface
M4RGMII1TXD11.8 VReduced Gigabit Media Independent Interface
J2RGMII1TXD21.8 VReduced Gigabit Media Independent Interface
L5RGMII1TXD31.8 VReduced Gigabit Media Independent Interface
J4RGMII1TX_CTL1.8 VReduced Gigabit Media Independent Interface
N2RGMII1RXC1.8 VReduced Gigabit Media Independent Interface
K4RGMII1RXD01.8 VReduced Gigabit Media Independent Interface
N3RGMII1RXD11.8 VReduced Gigabit Media Independent Interface
N4RGMII1RXD21.8 VReduced Gigabit Media Independent Interface
H1RGMII1RXD31.8 VReduced Gigabit Media Independent Interface
L3RGMII1RX_CTL1.8 VReduced Gigabit Media Independent Interface
N1RGMII1MDC1.8 VReduced Gigabit Media Independent Interface
M2RGMII1MDIO1.8 VReduced Gigabit Media Independent Interface
G2CANIN1.8 VController Area Network Interface
G3CANOUT1.8 VController Area Network Interface
G4CANSHDN1.8 VController Area Network Interface
D1JTAG0TDI3.3 VDebug JTAG
E2JTAG0TDO3.3 VDebug JTAG
C3JTAG0TCK3.3 VDebug JTAG
D2JTAG0TMS3.3 VDebug JTAG
C4JTAG0TRST3.3 VDebug JTAG
E1JTAG1TDI3.3 VSystem-Test JTAG
E3JTAG1TDO3.3 VSystem-Test JTAG
G5JTAG1TCK3.3 VSystem-Test JTAG
F3JTAG1TMS3.3 VSystem-Test JTAG
F2JTAG1TRST3.3 VSystem-Test JTAG
G12I2S0SCK1.8 VBit Clock
F13I2S0SWS1.8 VWord Select
G9I2S0SDI1.8 VData
G11I2S1SCK1.8V VBit Clock
G13I2S1SWS1.8 VWord Select
J13I2S1SDI1.8 VData
H11I2S2SCK3.3 VBit Clock
H12I2S2SWS3.3 VLeft/Right Clock
H13I2S2SDI3.3 VData
K13I2S3SCK3.3 VBit Clock
K12I2S3SWS3.3 VLeft/Right Clock
J11I2S3SDI3.3 VData
A2ADC0VIN_PanalogParallel HS-ADC0-VIN_P, LP-ADC-VIN_P, HP-ADC-VIN_P
A3ADC0VIN_NanalogParallel HS-ADC0-VIN_N, LP-ADC-VIN_N, HP-ADC-VIN_N
A4ADC1VIN_PanalogHS-ADC1-VIN_P
B1ADC1VIN_NanalogHS-ADC1-VIN_N
J3HYPERBUSCS01.8 VChip Select 0
J1HYPERBUSCS11.8 VChip Select 1
H3HYPERBUSCLK_P1.8 VDifferential Clock Positive
H2HYPERBUSCLK_N1.8 VDifferential Clock Negative
K2HYPERBUSRWDS1.8 VRead/Write Select
L2HYPERBUSDQ01.8 VData 0
K1HYPERBUSDQ11.8 VData 1
F6HYPERBUSDQ21.8 VData 2
D5HYPERBUSDQ31.8 VData 3
L1HYPERBUSDQ41.8 VData 4
K3HYPERBUSDQ51.8 VData 5
M1HYPERBUSDQ61.8 VData 6
G1HYPERBUSDQ71.8 VData 7
B4VIAL3-L2Through Package Via to Top Level
E4RESET3.3 VSystem Reset (Low Active)
J7VDD Digital1.8 VSupply
J8VDD Digital1.8 VSupply
K7VDD Digital1.8 VSupply
F4VDD Digital3.3 VSupply
F5VDD Digital3.3 VSupply
H4VDD Digital3.3 VSupply
H5VDD Digital3.3 VSupply
H6VDD Digital3.3 VSupply
J5VDD Digital3.3 VSupply
J6VDD Digital3.3 VSupply
K5VDD Digital3.3 VSupply
A9VDD Analog1.8VAnalog Sub-System Supply
B7VDD Analog1.8VAnalog Sub-System Supply
B8VDD Analog1.8VAnalog Sub-System Supply
C7VDD Analog1.8VAnalog Sub-System Supply
C8VDD Analog1.8VAnalog Sub-System Supply
C9VDD Analog1.8VAnalog Sub-System Supply
A6VSS AnalogAGNDAnalog Sub-System Ground
A7VSS AnalogAGNDAnalog Sub-System Ground
A8VSS AnalogAGNDAnalog Sub-System Ground
B5VSS AnalogAGNDAnalog Sub-System Ground
B6VSS AnalogAGNDAnalog Sub-System Ground
C5VSS AnalogAGNDAnalog Sub-System Ground
C6VSS AnalogAGNDAnalog Sub-System Ground
D8VSS DigitalGNDDigital Ground
D9VSS DigitalGNDDigital Ground
E8VSS DigitalGNDDigital Ground
E9VSS DigitalGNDDigital Ground
F9VSS DigitalGNDDigital Ground
G10VSS DigitalGNDDigital Ground
H9VSS DigitalGNDDigital Ground
H10VSS DigitalGNDDigital Ground
J9VSS DigitalGNDDigital Ground
K9VSS DigitalGNDDigital Ground
M6VSS DigitalGNDDigital Ground
N6VSS DigitalGNDDigital Ground
M5VSS BIAS DPUGNDDPU Bias Ground
N5VSS BIAS DPUGNDDPU Bias Ground
D3BOOT MODEBOOTM03.3 VBootloader settings
E5BOOT MODEBOOTM13.3 VBootloader settings
B3ReservedSet fix to GND
D6ReservedSet fix to GND
D4ReservedDon't connect
D4ReservedDon't connect
C1ReservedDon't connect
C2ReservedDon't connect
B2ReservedDon't connect
E6ReservedDon't connect
A5ReservedDon't connect
F1ReservedDon't connect

Power

IO voltage + Core voltage1.8V
IO voltage + MRAM3.3V
Maximum total power dissipation< 1W

Two different power domains and one reference voltage are required for the Ganymed® system. On Top-Level the IO voltages are available to supply the sensors and peripherals.

Power Distribution

Clocks

Low power operation clock/boot clock32.768kHz
System reference clock25MHz
System clocks (internal)Generated from external clock via PLL,
as required for functional units
CPU clock400MHz maximum

All clocks are integrated in the package. No external clock or oscillator is needed for the system. The CPU clock frequency can be set exclusively by the DAQU CPU core. All DPU cores operate at the same clock frequency (unless disabled), while the DAQU core frequency may be different.